--test rundy 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity test_sc0 is
    Port ( din : in  STD_LOGIC_VECTOR (7 downto 0);
		dout : out  STD_LOGIC_VECTOR (7 downto 0));
end test_sc0;


architecture Behavioral of test_sc0 is
component InSbox0set is
    Port ( si : in  STD_LOGIC_VECTOR (127 downto 0);
		so : out  STD_LOGIC_VECTOR (127 downto 0));
end component InSbox0set;

component Sbox0set is
    Port ( si : in  STD_LOGIC_VECTOR (127 downto 0);
		so : out  STD_LOGIC_VECTOR (127 downto 0));
end component Sbox0set;

signal sdin, sis, iso : STD_LOGIC_VECTOR (127 downto 0);
begin
sdin(7 downto 0) <=  din(7 downto 0);
sdin(127 downto 8) <= X"AFB3299C0A397BADD4A3C736294B45";

s: Sbox0set port map (sdin, sis);
ins: InSbox0set port map (sis,iso);

dout(7 downto 0)<=iso(7 downto 0);
end Behavioral;
